This invention relates to superconductive logic and memory circuits employing Josephson junction devices.
Josephson tunnel junctions appear to have a promising future in logic and switching applications. Most recent work has concentrated on hysteretic tunnel junctions used in a current-steering mode; i.e., a junction carrying a zero-voltage (V=0) current, I, derived from an external bias, is switched to V.noteq.0 by application of a control current. As a result, the bias current is diverted into a parallel path where it serves as a control current for one or more downstream junctions.
While switching from V=0 to V.noteq.0 is a well-understood process, the necessary complementary transition from V.noteq.0 to V=0 is less straightforward to implement. It generally requires the reduction of the junction current I below the "drop-back" current I.sub.o and/or the reduction of the junction voltage V below the corresponding voltage V.sub.o. Considerable work has been published on the AC powered latching mode of operation in which the junctions are reset to V=0 by momentarily decreasing the bias current from an external source to a sufficiently low value. In principle, however, DC powered circuitry seems less complicated. Several DC powered schemes, including a two-gate memory loop, have been described. In this configuration, the switching of one of the gates diverts its bias current into a parallel, zero-resistance path containing the second gate. Switching of the second gate then returns the bias current to the first gate in a symmetric manner.